1. Field Of The Invention
This invention relates to metal-oxide-silicon (MOS) devices and, more particularly, to a technique for fabricating and the consequent structure of n-channel MOS field effect transistors (FETs) and integrated circuits.
2. Prior Art
Over the years, refinements in the design and manufacture of MOS field-effect transistors and integrated circuits have given rise to major advances in the packing density of the finished devices. Techniques such as silicon-gate technology, wherein the gate electrodes are self-aligned to the source and drain regions, ion implantation and self-aligned field-doped thick field locally oxidized n-channel technology (see U.S. Pat. No. 3,751,722) have contributed greatly to the improvement in device density. However, as device packing densities have increased, so has the need for self-aligned contact holes. In n-channel field-doped, locally-oxidized silicon-gate MOS integrated circuits, for example, it would be highly desirable to form contact holes which are self-aligned to both the individual polycrystalline silicon (polysilicon) regions and to diffused regions formed in the so-called mesa regions which result from the use of recessed oxide regions within the integrated circuit. Ideally, a processing sequence is required wherein the placement of contact hole locations is relatively unaffected by photolithographic misalignment so that no extra area trade-off is required to compensate for misalignment.
In conventional silicon-gate technology, particularly in the fabrication of n-channel silicon-gate MOS integrated circuits, phosphosilicate glass has found widespread use as an intermediate dielectric insulating layer for separating the metallization layer from underlying regions of polysilicon and diffused single crystal silicon. The phosphosilicate glass has the advantage of smoothing abrupt contours which result from variations in film thickness and contact hole edges.
This is a result of phosphosilicate glass' ability to be turned into a viscous fluid at temperatures above about 1,000.degree. centigrade, thereby enabling it to "flow" over sharp polycrystalline silicon steps and dramatically improve the contour over which metalized interconnections will eventually run. The sharp contours would cause stress and cracks in the conductive metal films which electrically interconnect various parts of the device if the flowed phosphosilicate glass were not used.
There are, however, several disadvantages associated with the use of phosphosilicate glass. One such disadvantage is that it is chemically vapor deposited and, hence, is generally of non-uniform thickness and lower rupture strength than thermally grown silicon dioxide. This can be corrected by interposing a thin, thermally grown silicon dioxide layer between the underlying silicon and polysilicon layers and the phosphosilicate glass and subsequently etching oversized contact holes through this thin layer of silicon dioxide where desired. However, this procedure adds two additional steps to the manufacturing process. Another disadvantage associated with the use of phosphosilicate glass relates to its ability to react with water to form phosphoric acid which, in turn, can attack the aluminum metallization layer. Thus, moisture must be completely eliminated from the completed semiconductor device or significant reliability problems may result.
There have been attempts in the prior art to improve packing density, form self-aligned contact holes, and/or eliminate the use of phosphosilicate glass. One example was described by Muramoto et al. in a paper, entitled "A New Self-Aligning Contact Process for MOS/LSI" given at the 1978 International Electron Device Meeting in Washington, D.C. In this technique, an n-channel silicon-gate integrated circuit having a flat topology and high packing density is formed without the use of phosphosilicate glass. However, the manufacturing steps employed in this technique are extremely complex and the technique requires utilization of a new etching procedure called plasma-reactive sputter etching. In addition, other unconventional steps such as ion implantation through polysilicon and partial etching of thin layers of polysilicon are also required in this technique. The Muramoto et al technique requires a number of operations with manufacturing tolerances that would be difficult to meet in a production environment.
A simpler technique, which achieves relatively high packing density and avoids the use of phosphosilicate glass, is taught in Dingwall, U.S. Pat. No. 3,936,859. Dingwall teaches the use of silicon nitride to define the position of a silicon-gate structure and to protect the underlying polycrystalline silicon from oxidation. Since silicon nitride resists oxidation, it is possible to thermally grow thick local deposits of silicon dioxide around the gate in self-alignment with the gate edges. In Dingwall, however, only the contact hole to a gate electrode is self-aligned. No provision is made to simultaneously produce contact holes to enable subsequent high-density connections to single crystal diffused n+ regions.
Other approaches similar to Dingwall's are taught by V. L. Rideout et al in "MOSFETs With Polycrystalline Silicon-Gate Self-Aligned to the Field Isolation and to the Source/Drain Regions", 1976 International Electron Device Meeting, Section 24.1, Washington, D.C. and in "A One Device Memory Cell Using A Single Layer of Polysilicon And A Self-Registering Metal To Polysilicon Contact", 1977 International Electron Device Meeting, paper 13.2, Washington, D.C. Rideout et al also teaches the use of a layer of silicon nitride to prevent oxidation over the polysilicon gate and to reveal the entire gate area for contacting upon removal of the nitride. The structure taught by Rideout et al has the advantage of being doubly self-aligned because the polysilicon gate electrode is self-aligned on its ends with respect to the conductive source and drain regions and is also self-aligned on its sides with respect to the non-conductive field oxide isolation regions. However, as in Dingwall, the Rideout et al structure provides only for self-aligned contacts to the gate electrode while any contacts to single-crystal n+ diffused regions must be formed separately and are not self-aligned.